The present invention relates to a method and/or architecture for an analog envelope detector generally and, more particularly, to a method and/or architecture for detection of a modulated sinusoid wave with random phase in the presence of additive white Gausian noise.
Referring to FIG. 1, a system 10 is shown implementing a conventional analog envelope detector. An analog envelope detector can be implemented to detect a modulated sinusoid wave with random phase in the presence of white Gausian noise. The system 10 generally comprises a common mode detector circuit 12, a comparator 14, a comparator 16, an OR gate 18, a filter 20 and a buffer 22. A first input signal IN+ is presented to a first input of the common mode detector circuit 12 and a first input of the comparator 14. A second input signal INxe2x88x92 is presented to a second input of the common mode detector circuit 12 and a first input of the comparator circuit 16. The common mode detector circuit 12 presents a signal CM+THRE/2 to a second input of the comparator 14 and a signal CM-THRE/2 to a second input of the comparator 16. The common mode detector 12 is configured to determine the common mode voltage CM. The comparator 14 presents an output to a first input of the OR gate 18. Similarly, the comparator 16 presents a signal to a second input of the OR gate 18. The OR gate 18 presents a signal to the filter 20 which presents a signal to the buffer 22. The buffer 22 presents a signal OUT.
Referring to FIG. 2, a detailed diagram of the comparator 14 is shown. The comparator 14 comprises a number of resistors RL1-RL2 and a number of transistors Q1 and Q2. Each of the resistors RL1-RL2 is coupled to a power supply VPWR and the transistors Q1 and Q2, respectively. The comparator 14 also comprises a current source I. Emitters of the transistors Q1 and Q2 are coupled to the current source I. The current source I is also coupled to ground. The transistors Q1 and Q2 are configured as a differential pair. The transistor Q1 is controlled by a signal INPUT+ and is configured to control a voltage level of a node OUTxe2x88x92. The transistor Q2 is controlled by a signal INPUTxe2x88x92 and is configured to control a voltage level of a node OUT+.
In the conventional design shown in FIGS. 1 and 2, the common mode detector 12 internally calculates a common mode voltage (i.e., CM) of the input signals IN+ and INxe2x88x92. The common mode voltage CM and a threshold voltage (i.e., THRE) are used by the detector 12 to present the signals CM+THRE/2 and CM-THRE/2, which are DC threshold signals. The comparators 14 and 16 then perform a comparison between the two DC outputs CM+THRE/2 and CM-THRE/2 and the two differential inputs IN+ and INxe2x88x92.
Such conventional designs implement a small input impedance. Additionally, since the conventional design of FIGS. 1 and 2 implements NPN differential pair transistors (i.e., the transistors Q1 and Q2), the conventional design is not capable of operating when a voltage of the input signals IN+ and INxe2x88x92 is close to ground level.
It is therefore desirable to provide an analog envelope detector that may (i) detect an amplitude of an input data, (ii) increase an input impedance and/or (iii) be implemented without a common mode detector.
The present invention concerns a circuit configured to (i) receive a differential signal pair and a threshold signal and (ii) generate one or more common mode signals. The circuit generally provides a large impedance on each input line.
The objects, features and advantages of the present invention include providing a method and/or architecture for an analog envelope detector that may (i) detect an amplitude of an input data, (ii) increase an input impedance and/or (iii) be implemented without a common mode detector.